1. Technical Field
This invention generally relates to computer systems, and more specifically relates to the field of addressing schemes in computer systems.
2. Background Art
Computer systems have addressing capabilities that are defined by the computer hardware. The address space of a computer system is the range of addresses available to reference data, instructions, etc., and is determined by the size (in bits) of the address. The address size is one of the fundamental architectural features of a computer system. Early computer systems were single-user computers that could handle only a single task at a time, mapping all data into a single address space, and swapping data into and out of the address space whenever a new task needed to be performed. Later, computers were developed that supported multiple users and processes (or tasks). A computer system that supports multiple tasks must manage the allocation of the address space among the different tasks. That is, the effective addresses specified or computed by programs running in multiple tasks must be efficiently translated into real (physical) addresses used to access memory. More than one such address translation mechanism, or mode, may be provided by a single computer system. Examples of some address translation modes are given next.
Because the address space for all the tasks that might run on a computer system typically exceeds the system's physical address space size, a separate address space is typically allocated to each task, resulting in multiple virtual address spaces. This type of addressing is known as “local addressing”, because each task has its own virtual address space that is local to the process, and cannot be seen by other tasks.
Local address translation logic typically provides translation of effective addresses to virtual addresses, and virtual addresses to real (or physical) addresses using tables stored in memory and in registers in the processor. For example, a Segment Look aside Buffer (SLB) may be used to translate high-order bits of an effective address to high-order bits of a virtual address. In addition, address translation caches may be used to store recently-used address translations, thereby speeding execution of subsequent uses of the same translations. One type of address translation cache translates effective addresses directly to real addresses (ERAT). These caches speed computation by avoiding the two step process of translating an effective address to a virtual address and then translating the resulting virtual address to a real address. However, because effective address space values for different tasks typically must be translated to different virtual and real addresses, when an operating system switches from one task to another, the address translations must be changed, so nearly all of the cached local addressing translations must be invalidated as part of task switch processing. Note that a subset may be reserved by operating system convention for common use in more than one process or for use by the task switch code, so these entries need not be invalidated.
Another addressing mode used by some systems is a static or direct mapping between effective and virtual addresses, so the SLB is not used. For this addressing mode, all tasks share this portion of the effective address space. Thus a task switch does not change any part of the effective to real mapping, so ERAT entries derived from these translations remain valid.
More recently, computer systems have become capable of supporting multiple logical systems on the same hardware complex, through the use of a layer of firmware called a hypervisor. Each logical system image may be referred to as a partition. On such systems, the hypervisor must manage the hardware address translation facilities in a manner that strictly separates the address spaces used by different partitions, because each partition represents an independent system image. Another type of addressing mode supported by these systems is when the operating system thinks it is directly using real addresses, but in reality hardware features managed by a hypervisor interject some other form of address translation. These address translations are inherently global to a logical partition and so should survive task switches within a logical partition, but must be invalidated during partition switches. As a final example, hypervisor real address use is not affected by task switches or partition switches.
In known systems, task and partition switches typically perform a mass invalidation of address mappings, including invalidation of all entries in an effective to real address translation cache. Task switches are common and must typically invalidate the Segment Look aside Buffer (SLB) anyway, so this mass invalidation might be accomplished as a side-effect of an instruction that invalidates the SLB, for example. By performing a mass invalidation of entries in an effective to real address translation cache, the prior art systems implicitly assume that none of the address translations in the effective to real address translation cache will be valid after a task or partition switch. This assumption, however, is not correct, because some of the address translations in the effective to real address translation cache remain valid even after a task or partition switch. Without an effective apparatus and method for selectively invalidating entries in an address translation cache, the prior art will continue to suffer from the performance penalty that results from invalidating too many entries in an address translation cache, too frequently.